This invention relates to the art of traffic control devices and more particularly to an improvement in a digital coordinator for coordinating the signalization at a given intersection in a controlled traffic system.
The invention is particularly applicable for use in coordinating a multi-phase traffic flow pattern at a given intersection which is controlled by a remote master controller and it will be described with particular reference thereto; however, it is appreciated that the invention has much broader applications and may be used as a coordinator for various traffic control systems.
As is well known, traffic control systems often employ a master controller which can control the signalization at numerous intersections within a network or pattern of related traffic flow. Generally these systems utilize a coordinator at each intersection, which coordinator determines the background cycle length of the signalization and certain programmed functions for the controlled intersection. The master controller provides control information to the coordinator which, in turn, regulates the local controller in accordance with this and other input information. These coordinators include a means for determining the cycle length or duration for processing the total signalization cycle at the controlled intersection. In addition, outputs of the coordinator determine the length, spacing and existence of certain functions at the controlled intersection. Generally, this type of traffic system requires a means for providing a selected time offset of the background cycle of one intersection with respect to the background cycle of other intersections. Offset of a background cycle allows traffic flow in a more efficient manner along a continuous traffic flow pattern or grid. For instance, at certain times during the day, or during certain traffic conditions, it is necessary to change the offset at spaced intersections. To do this, a master synchronization pulse is created at the master controller. Each of the intersections then employs a selected time delay after the master pulse before its signalization cycle is initiated. As traffic conditions change, the offset is changed by the master controller to optimize traffic flow. This type of coordinated system is well known and is generally in use in traffic control systems.
In accordance with the present invention there is provided an improvement in the invention described and claimed in my prior application Ser. No. 663,580, filed Mar. 3, 1976. In the prior application a coordinator of the type described above, i.e. for creating a background cycle time used to control logic conditions for selected output circuits, includes a pulse counter for counting between N.sub.1 or 0 and N.sub.2 or 99 upon receipt of counting pulses. Output means are disclosed for creating signals upon counting to several of the digits in the range of 0 to 99. This previously described coordinator also includes means for controlling the frequency of the counting pulses to a frequency of one hundred divided by the time of the desired background cycle is seconds and decoding means for creating the selected output logic conditions in the output circuits when the counter counts to a selected number in the range of 0 to 99. In this manner, there is created a background cycle which is advanced by a selected percentage between 0 and 99 in a digital fashion. This incremented background cycle is divided into one hundred increments representing percentages of the background cycle, irrespective of its adjusted time or length of the cycle. The cycle time or duration can be adjusted by changing the input counting frequency of the pulse counter.
The present invention relates to an improvement in the basic digital coordinator described in the previously mentioned copending application. In accordance with the present invention, there is provided a digital system for synchronizing the background cycle with respect to a signalization offset signal sent from the master controller. It is often necessary to adjust the offset of a traffic signalization cycle with respect to other coordinated traffic signals. In such a system, an offset signal is created at the various intersections which offset signal has a preselected time spacing with respect to a master synchronization signal. During normal operations, the background cycle of the digital coordinator corresponds with the existing offset signal. If the offset signal is changed, the digitally produced background cycle no longer corresponds to, i.e. is not synchronized with, the new position of the offset signal. Thus, it is necessary to adjust the background cycle to again correspond to, or be synchronized with, the new position of the offset signal. In addition, if for any reason, there is drift in the background cycle, it is advisable to readjust the background cycle to correspond with the desired offset determined by the offset signal from the master controller.
The present invention relates to an improvement in a digital controller wherein a changed relative time position of the offset signal from the master controller can be acknowledged and the background signal can be shifted to the desired relative time position without undue interruption of signalization at any given intersection. In other words, when the offset signal is substantially spaced from the start of an existing background cycle, resynchronization is obtained by digitally synchronizing subsequent background cycles in a gradual manner and without unduly changing a single signalization background cycle.
In accordance with the present invention, there is provided an improvement in a digital coordinator of the type described above, which improvement includes means for digitally measuring the time period between the N.sub.1, or first, control pulse of the background cycle and the occurrence of one of the signalization offset signals during a given background cycle and then means for stopping the control pulses to the main cycle counter for the measured time period. In addition, this stopping action for the pulse counter can occur only when the signalization offset signal is within a preselected percentage range of the initial pulse in an existing background cycle. Otherwise, there is provided means for increasing or decreasing the pulse counting rate used in creating the background cycle to shift the background cycle gradually toward a synchronization condition.
By utilizing the present invention, a change in offset can be gradually compensated for by the present invention to shift gradually the existing background cycle to ultimately correspond with the signalization offset signal.
The primary object of the present invention is the provision of a system in a digital traffic coordinator, which system digitally synchronizes the background cycle with a signalization offset signal with a gradual operation, except near actual synchronization conditions.
Another object of the present invention is the provision of a system as described above, which system can be adapted to various digital coordinators for use in traffic control.
These and other objects and advantages will become apparent from the following description taken together with the accompanying drawings.